In general, as semiconductor devices become more highly integrated, the importance of metal lines increases. Specifically, in a logic design technique as well as a memory design technique, the use of a back end of line (“BEOL”) process becomes greater than that of a front end of line (“FEOL”) process. This trend has caused a decrease in the operating speeds of semiconductor devices due to increases in resistance and parasitic capacitance upon formation of the metal lines.
For example, U.S. Pat. No. 6,448,649 discloses a method of forming plugs of two layers by deposition of a material for the plugs into holes and U.S. Pat. No. 6,130,102 discloses a method of forming plug of a dual damascene type to prevent a leakage current in a capacitor. However, such conventional methods cause structural problems and result in a high manufacturing cost of the semiconductor device.